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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Configuration Registers
Two user-accessible configuration registers define the device operation. The bus config-
uration register (BCR) defines how the CellularRAM interacts with the system memory bus
and is nearly identical to its counterpart on burst mode Flash devices. The refresh configu-
ration register (RCR) is used to control how refresh is performed on the DRAM array.
These registers are automatically loaded with default settings during power-up and can
be updated any time the devices are operating in a standby state.
Access Using CRE
The configuration registers are loaded using either a synchronous or an asynchronous
WRITE operation when the configuration register enable (CRE) input is HIGH (see
Figure 13 on page 19 and Figure 14 on page 20). When CRE is LOW, a READ or WRITE
operation will access the memory array. The register values are placed on address pins
A[19:0]. In an asynchronous WRITE, the values are latched into the configuration
register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB#
are “Don’t Care.” Access using CRE is WRITE only. The BCR is accessed when A[19] is
HIGH; the RCR is accessed when A[19] is LOW.
Figure 13:
Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY
Operation
C LK
A[18:0]
OP C ODE
tAV S
S ele c t C ontrol Re g ister
tAVH
ADDRE SS
A19 1
C RE
ADV#
tVPH
tAV S
tAVH
ADDRE SS
tVP
t C PH
C E#
Initiate C ontrol Re g ister A cc ess
t C W
OE#
tWP
WE#
LB#/UB#
DQ[15:0]
Note:
Write A dd ress Bus Value
to C ontrol Re g ister
A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
DATA VALID
DON’T C ARE
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2005 Micron Technology, Inc. All rights reserved.
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